UVM Verification specialist

About role - We are seeking highly skilled UVM Verification specialists to join our dynamic team and support cutting-edge projects in the telecom sector.

This is an opportunity to work on complex ASIC and FPGA designs , leveraging advanced verification methodologies to ensure world-class quality and performance.

Key Responsibilities: Perform ASIC Verification using UVM and SystemVerilog .

Develop and execute test plans , test benches , and Verification environments .

Work on IP block Verification and multi-clock domain designs .

Collaborate with design teams to ensure functional correctness and coverage goals.

Apply formal Verification techniques and contribute to continuous improvement of verification processes.

Debug and resolve issues efficiently under tight timelines.

Minimum 7 years of experience in ASIC/FPGA Verification.

Strong expertise in UVM methodology and SystemVerilog .

Hands-on experience with complex ASIC or large FPGA designs .

Experience in multi-clock domains and IP block Verification .

Knowledge of formal Verification tools and techniques.

Ability to create comprehensive and complex coverage models.

Can write immediate and concurrent assertions.

Familiar with common protocols such as AXI, AXIS, Avalon-MM, Avalon-ST, AHB, APB, Ethernet.

Analytical mindset, results-oriented, and ability to work independently while being a strong team player.

Experience in developing verification test benches from scratch.

Preferable: Experience with C , emulation , Python, Perl, Bash and/or HLS .

Preferable: Strong constrained randomization skills.

Preferable: Telecom experience.