Staff/ Sr Staff Engineer, STA

We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis .

You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.

Key Responsibilities Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists.

Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization).

Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets.

Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist.

UPF management for multiply power domains.

Timing Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools.

Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.

Constraint Development: Architect, validate, and manage files, addressing both functional and DFT modes.

Develop and manage comprehensive block-level and top-level constraints (SDC / UPF).

Low-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies

Experience of about 8-13 years in synthesis and STA closure.

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle.

Extensive experience in STA closure on complex design with ability to understand the clocks structure from both functional and DFT side and provide solutions to complete design closure.

Worked on synthesis of high frequency designs and come up PPA solutions to meet the targets.

Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC.

Strong understanding of static timing analysis, power analysis, and signal integrity analysis.

Excellent problem-solving skills and attention to detail.

Excellent scripting skills and development of utilities to reduce overall TAT.

Ability to work effectively in a team environment and communicate clearly with cross-functional teams.

Experience in mentoring and coaching junior engineers is a plus.