Power-Domain Verification Lead

Verification Lead Power Aware Simulation position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience in power aware simulations with UPF verification and UVM testbench development.

You will be responsible for RTL SoC/Subsystem verification based on ARM CPUs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows.

You will report to the Director of Engineering, Verification.

Key Responsibilities Execute power-aware simulations and debug failures related to power intent Integrate UPF with UVM testbenches and VIPs Expertise in verifying design at RTL (SOC) level and gate-level simulation Create directed and constrained-random tests for low-power scenarios Verify: Power gating Isolation Retention save/restore Reset behavior across power domains Develop assertions and functional coverage for power states and transitions Support power-aware regression and sign-off Fluency with scripting languages (e.g., Make, Perl, Python, Shell) Collaborating with RTL, power architects

10+ years of experience with strong hands-on experience with SystemVerilog & UVM Solid understanding of UPF / power intent modeling Experience with power-aware simulation Knowledge of: Power domains & power states Isolation, retention, level shifters Reset vs power interactions Strong debug skills across RTL, UPF, and testbench ACADEMIC CREDENTIALS BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent