Sr. Staff Engineer - Physical Design

We are seeking an experienced and highly technical Backend Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs.

You will own the complete RTL-to-GDSII flow, focusing heavily on power recovery, clock tree optimization, and pushing aggressive PPA metrics on advanced technology nodes Key Responsibilities RTL-to-GDSII Execution: Own and drive the end-to-end physical design implementation, including floor planning, synthesis, placement, Clock Tree Synthesis (CTS), and routing.

PPA Optimization: Fine-tune the design to meet stringent Power, Performance, and Area (PPA) targets.

Employ advanced techniques like multi-voltage domains, power gating (UPF), and datapath optimization to minimize power while maximizing speed.

Timing Closure & STA: Drive Static Timing Analysis (STA) across multiple corners and operating modes.

Resolve setup/hold violations, signal integrity issues, and clock domain crossing constraints.

Physical & Formal Verification: Execute Design Rule Checks (DRC), Layout Versus Schematic (LVS), electromigration/IR drop (EMIR) analysis, and Equivalence Checking (LEC/Formality) to ensure design reliability and manufacturability.

Cross-Functional Collaboration: Work closely with RTL (Frontend), DFT, and Signoff teams to iterate on designs and structural changes for optimal PPA.

Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies

Experience of about 10+ years in Physical design implementation Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle.

Extensive experience in physical design PPA activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure.

Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk.

Strong understanding of static timing analysis, power analysis, and signal integrity analysis.

Excellent problem-solving skills and attention to detail.

Ability to work effectively in a team environment and communicate clearly with cross-functional teams.

Experience in mentoring and coaching junior engineers is a plus.