Principal Engineer , DFT

Renesas is seeking a highly experienced Principal DFT Engineer to drive end-to-end DFT execution for advanced SoCs/MCUs.

The candidate should possess deep expertise across the complete DFT lifecycle, from test architecture definition through silicon bring-up and production test deployment.

Key Responsibilities Define and drive SoC-level DFT architecture and test strategy, including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression.

Own the complete DFT flow from test architecture, RTL design & integration, DFT verification, scan insertion, ATPG, coverage closure, and signoff.

Drive silicon bring-up, silicon debug, diagnosis, yield improvement, and production test enablement.

Develop and deploy scalable DFT methodologies, automation frameworks, and best practices.

Collaborate with Design, Verification, Physical Design, and Test Engineering teams.

Provide technical leadership and mentor engineers across projects.

B.E./B.Tech., M.E./M.Tech., or Ph.D. in Electronics or related field. 15+ years of hands-on DFT experience with successful delivery of multiple SoCs.

Proven expertise in: DFT Architecture & Test Planning DFT RTL Design & Integration Scan Insertion & ATPG MBIST, LBIST, JTAG/IJTAG GLS & Signoff Silicon Bring-up, Debug & Diagnosis Strong hands-on experience with Tessent, Genus/Fusion Compiler, VCS/Xcelium, and Conformal/Formality.

Strong automation and scripting skills using Python, TCL, Perl, or Shell.

Leadership & Soft Skills Strong technical leadership with the ability to influence cross-functional and global teams.

Demonstrated ownership, accountability, and execution excellence.

Excellent analytical, problem-solving, and debugging skills.

Proven mentoring and coaching capabilities to develop engineering talent.

Self-motivated, collaborative, and results-oriented with a continuous improvement mindset.