Senior Principal Engineer, Silicon Photonics Architect

Lead the architecture and provide guidance for technical execution of photonic integrated circuit (PIC) and electronic integrated circuit (EIC) platforms, delivering pilot projects that prove technology feasibility, system value, manufacturability, and a path to productization.

Job Summary Own end-to-end architecture for silicon photonics solutions that combine PICs, EICs, advanced packaging, optical interfaces, firmware, and system-level control.

Translate product, customer, and business requirements into system architecture, technical specifications, performance budgets, interfaces, technology choices, and executable pilot plans.

Define and deliver pilot demonstrators that de-risk critical capabilities such as optical I/O, co-packaged optics, chiplet connectivity, sensing, or other strategic silicon-photonics use cases.

Provide technical leadership across concept, modeling, design, tape-out, packaging, bring-up, characterization, and proof-of-value demonstrations.

Build a pragmatic roadmap from prototype to scalable products, including platform reuse, ecosystem choices, and make/buy/partner recommendations Define system requirements and partition functionality across PIC, EIC, package, substrate/interposer, optics, firmware, and host interfaces Create link and system budgets covering optical loss, laser power, modulation, receiver sensitivity, signal integrity, power, thermal behavior, latency, reliability, and testability Guide PIC architecture and design tradeoffs involving modulators, photodetectors, waveguides, couplers, filters, splitters, monitors, and calibration structures Guide EIC architecture and tradeoffs involving laser/modulator drivers, TIAs, clocking/CDR, SerDes interfaces, ADC/DAC or control loops, telemetry, power management, and digital control Lead architecture reviews and design reviews; establish interface specifications, verification plans, risk registers, success criteria, and measurable pilot exit gates.

Coordinate foundries, OSAT/advanced-packaging partners, IP vendors, EDA/tool providers, laboratories, and university or ecosystem collaborators Partner with product, software, design, verification, packaging, test, reliability, manufacturing, and business teams to achieve performance, cost, schedule, and quality objectives Mentor architects and engineers, raise technical capability across the organization, and communicate recommendations clearly to senior technical and business leaders.

Contribute to invention disclosures, patents, technical publications, supplier assessments, and longer-term silicon-photonics technology strategy

BTech/BE, MTech/ME, or PhD in Electrical Engineering, Electronics, Photonics, Applied Physics, Computer Engineering, or a related field with hardware engineering experience of 15+ years Deep expertise in silicon photonics, optical communications, photonic integration, electro-optic systems, or closely related semiconductor technologies Proven experience architecting or delivering at least one complex PIC/EIC, optical transceiver, optical I/O, co-packaged optics, or integrated photonics program from concept through silicon or hardware validation.

Strong understanding of PIC building blocks and passive/active optical behavior, supported by modeling, simulation, laboratory characterization, and data-driven design tradeoffs.

Strong understanding of high-speed mixed-signal EIC functions and the electrical/optical interfaces between drivers, modulators, photodetectors, TIAs, clocking, control, and digital logic.

Working knowledge of semiconductor process technologies, PDK-based design, DFM, process variation, yield, reliability, thermal constraints, packaging, assembly, and production test.

Ability to use or direct use of photonic, electromagnetic, circuit, link, thermal, and signal-integrity simulation tools; ability to correlate models with measured results.

Excellent problem-solving, written and verbal communication, technical influence, teamwork, attention to detail, and commitment to execution quality.

Prior experience with technologies and standards relevant to high-speed links, such as Ethernet/IEEE, OIF CEI, PCIe/CXL connectivity, SerDes, FEC, and system management interfaces Any of following experience would be a plus : Co-packaged optics, optical I/O chiplets, pluggable optical modules, data-center interconnect, AI/HPC fabrics, or high-speed Ethernet applications, Advanced packaging such as 2.5D/3D integration, interposers, hybrid bonding, flip-chip, fiber attach, laser integration, thermal solutions, and package-level optical/electrical co-design