Pre-Silicon SoC Validation - Technical Lead

Job Details: Job Description: Role Summary: Seeking an experienced SoC Validation Engineer to define, drive, and execute validation strategies across the full silicon lifecycle, from architecture definition and pre-silicon planning through silicon power-on, post-silicon debug, stepping readiness, and PRQ quality convergence.

The role requires deep expertise in complex SoC validation, security validation, coherency flows, firmware and hardware interaction, disaggregated architecture, and cross-functional technical leadership.

The engineer will be responsible for ensuring early risk identification, high-quality milestone readiness, predictable silicon bring-up, rapid sighting debug, and continuous feedback from post-silicon learnings into earlier validation phases.

Key Responsibilities: Define and drive end-to-end SoC validation strategy across the full lifecycle, including architecture definition, pre-silicon validation planning, RTL milestone readiness, silicon power-on preparation, post-silicon debug, stepping readiness, and PRQ quality convergence.

Develop comprehensive validation plans, execution strategies, coverage goals, debug plans, and sign-off criteria aligned to program milestones and product quality targets.

Drive validation of critical SoC flows across security, coherency, memory, fabric, IO, and cross-die interactions in disaggregated architectures.

Validate complex hardware, firmware, and software interactions with specific focus on security handshakes, coherency protocols, cache and fabric ordering, access control, isolation, attestation, fuse/security policy behavior, and multi-die/domain interactions.

Review architecture and microarchitecture specifications to identify validation gaps in security, coherency, shared-resource behavior, cross-die communication, firmware sequencing, and lifecycle readiness from pre-silicon through post-silicon execution.

Drive debug of complex pre-silicon and post-silicon failures, identify root cause across RTL, firmware, microcode, platform software, validation content, security policy, coherency behavior, and system-level configuration.

Partner with architecture, design, verification, firmware, post-silicon, security, coherency, platform, manufacturing, and program teams to ensure high-quality validation readiness, silicon bring-up efficiency, and timely closure of issues across product milestones.

Use post-silicon sightings, customer issues, stepping feedback, defect trends, security observations, and coherency escapes to strengthen earlier validation strategies, improve coverage, and prevent repeated escapes across programs.

Define validation quality metrics, execution dashboards, risk indicators, milestone readiness reports, and sign-off recommendations for leadership reviews.

Drive innovation in validation efficiency, including automation, test grading, coverage-driven execution, AI/ML-assisted bug hunting, regression optimization, and shift-left methodologies.

Mentor senior and mid-level engineers, build technical depth in the team, and contribute to reusable validation methodologies, collateral, and best practices across programs.

Qualifications: Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, VLSI, Embedded Systems, Computer Science, or a related discipline. 12-20 years of relevant industry experience in pre-silicon validation, SoC validation, design verification, silicon validation, firmware validation, or hardware/software co-validation.

Strong understanding of SoC architecture, microarchitecture, CPU/core integration, fabrics, memory subsystem, security, coherency, cache hierarchy, firmware-driven security flows, and disaggregated/multi-die architectures.

Hands-on experience defining and executing validation strategies across the product lifecycle, including architecture review, pre-silicon planning, RTL milestone readiness, silicon power-on preparation, post-silicon sighting debug, stepping feedback, and PRQ quality convergence.

Proven experience in developing validation plans, test strategies, debug methodologies, coverage closure plans, post-silicon feedback loops, and milestone sign-off criteria for complex SoCs and disaggregated silicon products.

Required Technical Skills: Deep knowledge of SoC architecture, system architecture, disaggregated and multi-die architecture, microarchitecture fundamentals, IP/subsystem integration, fabrics, memory hierarchy, and cross-die communication.

Strong expertise in validation methodologies across the pre-silicon to post-silicon continuum, including test planning, content development, coverage closure, milestone readiness, silicon bring-up support, sighting reproduction, and lifecycle feedback loops.

Strong technical depth in security validation, coherency validation, cache/fabric ordering, access-control flows, isolation mechanisms, firmware-authenticated flows, fuse/security policy behavior, and multi-domain system interactions.

Strong debug skills using waveform analysis, logs, traces, checkers, assertions, firmware instrumentation, and platform-level debug tools.

Experience with one or more programming or scripting languages such as C, C++, Python, Perl, SystemVerilog, UVM, or similar validation automation languages.

Knowledge of firmware and microcode flows, manageability firmware, or other SoC firmware interactions.

Understanding of validation quality metrics, functional coverage, test effectiveness, regression health, bug trends, and milestone readiness indicators.

Leadership and Collaboration Expectations Operate as a senior technical leader who can independently define technical direction, influence stakeholders, and drive convergence across multiple teams.

Lead cross-functional discussions with architecture, design, verification, firmware, post-silicon, platform, manufacturing, and program management teams.

Identify program risks early, propose mitigation plans, and drive technical decision-making to protect milestone predi