Principal Engineer. Virtual Prototype Modeling

Virtual Prototype development for SoC and Electronics Systems for the purpose of embedded software development SystemC modeling experts for Virtual Prototype development, verification & deployment.

Roles & Responsibilities: Developing SystemC/TLM2.0 based models of IP blocks, CPU, SoC, System Defining transaction level models of Processors/Cache controllers/Interconnects/Peripherals/NPU/ISP Porting OS on the virtual prototype, developing the device drivers etc.

Verification of models at IP & SoC level Develop regressable self checking test suites using C/ARM assembly Develop System Level Flows and Methodologies using virtual prototypes Support the firmware and SW teams in effectively using the virtual prototypes

MTech/BTech in EE/CS with hardware engineering experience of 15+ years.

Proficiency in C / C++ / System C , Data structures, Algorithms, Object oriented programming Experience in developing SystemC, TLM based models for the virtual platform of an SoC Expertise in creating Virtual Prototype of SoC or electronics systems Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS etc..) Validation of virtual prototypes, writing bare metal tests, Embedded tool chain, assembly language, debugging knowledge, embedded Linux Knowledge of Microprocessor, Microcontrollers, SoC architecture, bus protocols etc.

Knowledge of Computer and Processor Arch (including Caches, MMU, Pipeline) Should have exposure to quality processes for project execution, delivery, and working with multiple teams across geos Excellent problem-solving skills Experience in application development in assembly or higher-level languages Preferred Expertise: IP-XACT, SystemRDL, SystemC-AMS